1. Field of the Invention
The present invention relates to a semiconductor device, a method of generating a semiconductor device, a method of manufacturing a semiconductor device and a device for generating a semiconductor device. More particularly, the present invention relates to a generation of a pattern used for a semiconductor device capable of generating a highly accurate pattern according to a process condition of the semiconductor device and also capable of flattening a surface of the pattern.
2. Description of Related Art
Recently, semiconductor devices, especially, large-scale integrated circuits (LSI) have been increasingly made fine and the grade of integration has been enhanced. Accordingly, there is a strong and growing demand for forming a fine and complicated pattern. In these circumstances, in order to form a pattern in accordance with the design, the process condition is increasingly restricted. In the case of forming a semiconductor device, a surface of a semiconductor substrate is subjected to isolation and at the same time a well of a predetermined density is formed, and a desired conductive type impurity diffusion region is formed in the well. Further, an insulating film and a wiring pattern are formed.
For example, the wiring pattern is formed as follows. After a conductive layer such as a polycrystalline silicon layer, an aluminum layer and a metallic silicide layer has been formed, a desired mask pattern is formed by photolithography, and etching is conducted while this mask pattern is used as a mask. In this way, the wiring pattern can be formed.
In the etching process, a conductive film exposed from the mask pattern is selectively removed. However, even when the concentration and temperature of the etchant are optimized, the etching speed fluctuates by the influence of the pattern density (area ratio) and the peripheral length of the mask pattern. Therefore, according to the density or the pattern pitch of the mask pattern, the etching accuracy becomes different. Accordingly, the etching accuracy deteriorates even when the mask pattern region is too large or too small.
In the case of forming the diffusion layer, the same problems may be encountered. When a region into which ions are injected is too small in the case of forming the diffusion layer, ions are concentrated, and it is impossible to obtain a predetermined diffusion profile.
A method of CMP (Chemical Mechanical Etching) is proposed for flattening a substrate surface. According to this method, after an insulating film has been formed on the surface, for example, by the coating method or CVD method, chemical etching is conducted while mechanically polishing, so that the surface can be flattened. However, in the case where the pattern density of the lower wiring layer is small, when a region, in which a pattern of not less than a predetermined area does not exist, is existing, even if a thick insulating layer is formed, it is impossible to flatten the surface. As a result, even after CMP has been conducted, a recess portion in which no wiring pattern exists is formed, that is, the surface is left being recessed.
In the case where the layout pattern is biased as described above, the following problems may be encountered. Not only it is impossible to obtain sufficiently high pattern accuracy with respect to the layer concerned but also the pattern accuracy of an upper layer of the layer concerned is affected. Therefore, it is impossible to obtain sufficiently high process accuracy.
In the above circumstances, LSI is positioned as a key device of each product. In order to enhance the competitiveness of products, there is a demand of increasing the scale and the processing speed of LSI. Since the product cycle has been recently shortened, in order to meet the demand, it indispensable to automatically conduct to design LSI.